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HI7188
August 1997
8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System
Description
The HI7188 is an easy-to-use 8-Channel sigma-delta programmable A/D subsystem ideal for low frequency physical and electrical measurements in scientific, medical, and industrial applications. The subsystem has complete on-chip capabilities to support moving the intelligence from the system controller and towards the sensors. This gives the designer faster and more flexible configurability without the traditional drawbacks of low throughput per channel, higher power or cost per channel. Extreme design complexity and excessive software overhead is eliminated. The HI7188 contains a fully differential 8 channel multiplexer, Programmable Gain Instrumentation Amplifier (PGIA), 4th order sigma-delta ADC, integrating filter, line noise rejection filters, calibration and data RAMs, clock oscillator, and a microsequencer. Communication with the HI7188 is performed via the serial I/O port, and is compatible with most synchronous transfer formats, including both the Motorola/Intersil 6805/11 series SPI, QSPI and Intel 8051 series SSR protocols. The powerful on-board microsequencer provides automatic conversions on the multiplexed input channels (up to 8) by controlling all channel switching, filtering and calibration. The microsequencer supports on-the-fly multiplexer reconfiguration, forty to fifty times faster throughput than the competition and zero step response delay during internal or external multiplexer channel changes. A simple set of commands gives the user control over calibration, PGIA gain, and bipolar/unipolar modes on a per channel basis. Number of channels to convert, data coding, line noise rejection, etc. is programmed at the chip level. The calibration RAMs allow the user to read and write system calibration data while the data RAMs provide a read support of the conversion results for each channel. This design is effectively eight 16-bit (for 96dB noise-free dynamic range) Sigma-Delta A/D converters combined with a microsequencer and an eight-channel multiplexer in a single package. The HI7188 provides 120dB line-noise rejection at 240 samples/second/channel (in 60Hz line-rejection mode) and 200 samples/second/channel (in 50Hz line-rejection mode) base output data rates. By reusing multiplexer channels for the same input, throughput can increase by integer increments of the base output data rate up to 1920Hz.
Features
* Fully Differential 8-Channel Multiplexer and Reference * Automatic Channel Switching with Zero Latency * 240 Conversions Per Second Per Channel * 16-Bit Resolution with No Missing Codes * 0.0015% Integral Non-Linearity * Fully Software Configurable - -120dB Rejection of 60/50Hz Line Noise - Channel Conversion Order and Number of Active Channels - True Bipolar or Unipolar Input Range Per Channel - PGIA Gain Per Channel - 2-Wire or 3-Wire Interface * Chopper Stabilized PGIA with Gains of 1 to 8 * Serial Data I/O Interface, SPI Compatible * 3 Point System Calibration * Low Power Dissipation of 30mW (Typ)
Applications
* Multi-Channel Industrial Process Controls * Weight Scales * Medical Patient Monitoring * Laboratory Instrumentation * Gas Monitoring System * Reference Literature - AN9504 "A Brief Introduction to Sigma Delta Conversion" - TB329 "Intersil Sigma-Delta Calibration Techniques" - AN9518 "Using the HI7188 Evaluation Kit" - AN9610 "Interfacing the HI7188 to a Microcontroller" - AN9538 "Using the HI7188 Serial Interface"
Ordering Information
PART NUMBER HI7188IP HI7188IN HI7188EVAL TEMP. RANGE (oC) -40 to 85 -40 to 85 25 PACKAGE 40 Ld PDIP 44 Ld MQFP Evaluation Kit PKG. NO. E40.6 Q44.10x10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
4016.4
7-1847
HI7188 Pinouts
HI7188 (PDIP) TOP VIEW
MODE SCLK SDO SDIO OSC1 OSC2 DVDD DGND AVSS VINL1 VINH1 VINL2 VINH2 VINL3 VINH3 VINL4 VINH4 VINL5 VINH5 VINL6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 CS 39 RSTI/O 38 EOS 37 A2 36 A1 35 A0 34 MXC 33 CA 32 RST 31 DGND 30 AVSS 29 AVDD 28 VRHI 27 VRLO 26 VCM 25 VINH8 24 VINL8 23 VINH7 22 VINL7 21 VINH6
HI7188 (MQFP) TOP VIEW
RSTI/O
MODE
DGND
SCLK
SDIO
SDO
EOS
CS
A2
A1
OSC1 OSC2 DVDD DGND AVSS AVSS VINL1 VINH1 VINL2 VINH2 VINL3
1
44 43 42 41 40 39 38 37 36 35 34 33 2 32 3 4 5 6 7 8 9 31 30 29 28 27 26 25 24
A0
MXC CA RST DVDD DGND AVSS AVSS AVDD VRHI VRLO VCM
10
11 23 12 13 14 15 16 17 18 19 20 21 22
VINH3
VINH4
VINH5
VINH6
VINH7
7-1848
VINH8
VINL4
VINL5
VINL6
VINL7
VINL8
Functional Block Diagram
VCM 16 LOGICAL CHANNELS LINE NOISE FILTER RAM0 CH1 CH2 CH3 23 CH4 CH5 CH6 CH7 CH8 MODE 24 16 CH7 CH8 CH6 CH5 CH4 24 CH4 CH5 CH6 CH7 CH8 CH3 CH3 CH2 CALIBRATION REGISTERS AND CONTROL CH1 BYPASS LNR
VRHI VRLO
PHYSICAL CHANNELS
RAM1
CH1 CH2
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
VIN1H VIN2H VIN3H VIN4H VIN5H VIN6H VIN7H VIN8H 4TH ORDER 1 INTEGRATING FILTER
PGIA
-
MODULATOR
HI7188
MXC CCR REGISTERS
LOGICAL SEQUENCER
7-1849
EOS CA
PGIA GAIN
VIN1L VIN2L VIN3L VIN4L VIN5L VIN6L VIN7L VIN8L
BIPOLAR/UNIPOLAR
CHANNEL SELECT
CONVERSION CONTROL
A0 A1 A2
LOGICAL CHANNEL ADDRESS
SERIAL INTERFACE CONTROL REGISTER CLOCK GENERATOR
OSC1 OSC2
RST MODE
CS
SCLK SDO SDIO RSTIO
HI7188 Typical Application Schematic
3.6864MHz 17 +5V R1 0.1F 29 + 4.7F 16 + 4.7F 0.1F +5V
AVDD OSC1 OSC2 DVDD
HI7188IP
28 27 11 10 13 12 15 14 17 16 18 17 21 20 23 22 25 24 26 9, 30 VRHI VRLO VINH1 VINL1 VINH2 VINL2 VINH3 VINL3 VINH4 VINL4 VINH5 VINL5 VINH6 VINL6 VINH7 VINL7 VINH8 VINL8 VCM MODE AVSS DGND 8, 31 MXC A2 A1 A0 EOS CA RST SCLK SDIO SDO
+2.5V REFERENCE
2 4 DATA I/O 3 DATA OUT
+ CHANNEL 1
+
CHANNEL 2
+
39 RSTI/O 40 CS 38 EOS 33 32 RST 34 37 36 35 MXC A2 A1 A0 CA CS RSTI/O
CHANNEL 3
+
CHANNEL 4
+
CHANNEL 5
+ CHANNEL 6
+
CHANNEL 7
+
CHANNEL 8
-
1
-5V 0.1F + 4.7F +
7-1850
HI7188 Pin Descriptions
40 LEAD PDIP 1 2 3 4 5 44 LEAD MQFP 41 42 43 44 1 PIN NAME MODE SCLK SDO SDIO OSC1 PIN DESCRIPTION Mode input. Used to select between Synchronous Self Clocking (MODE = 1) or Synchronous External Clocking (MODE = 0) for the Serial Port. Serial interface clock. Synchronizes serial data transfers. Data is input on the rising edge and output on the falling edge. Serial Data Out. Serial data is read from this line when using a 3-wire serial protocol such as the Motorola Serial Peripheral Interface. Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial Interface using a 2-wire serial protocol. Oscillator clock input for the device. A crystal connected between OSC1 and OSC2 will provide a clock to the device, or an external oscillator can drive OSC1. The oscillator frequency should be 3.6864MHz to maintain Line Noise Rejection. Used to connect a crystal source between OSC1 and OSC2. Leave open otherwise. Positive Digital supply (+5V). Digital supply ground. Negative analog power supply (-5V). Analog input low for Channel 1. Analog input high for Channel 1. Analog input low for Channel 2. Analog input high for Channel 2. Analog input low for Channel 3. Analog input high for Channel 3. Analog input low for Channel 4. Analog input high for Channel 4. Analog input low for Channel 5. Analog input high for Channel 5. Analog input low for Channel 6. Analog input high for Channel 6. Analog input low for Channel 7. Analog input high for Channel 7. Analog input low for Channel 8. Analog input high for Channel 8. Common mode voltage. Must be tied to the mid point of AVDD and AVSS. External reference input. Should be negative referenced to VRHI. External reference input. Should be positive referenced to VRLO. Positive analog power supply (+5V). Active low Reset pin. Used to initialize modulator, filter, RAMs, registers and state machines. Calibration active output. Indicates that at least one active channel is in a calibration mode. Multiplexer control output. Indicates that the conversion for the active channel is complete. Logical channel count output (LSB). Logical channel count output. Logical channel count output (MSB). End of scan output. Signals the end of a channel scan (all active channels have been converted) and data is available to be read. Remains low until data RAM is read. I/O reset (active low) input. Resets serial interface state machine only. Active low chip select pin. Used to select a serial data transfer cycle. When high the SDO and SDIO pins are three-state.
6 7 8, 31 9, 30 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 36 37 38 39 40
2 3, 30 4, 29, 39 5, 6, 27, 28 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 31 32 33 34 35 36 37 38 40
OSC2 DVDD DGND AVSS VINL1 VINH1 VINL2 VINH2 VINL3 VINH3 VINL4 VINH4 VINL5 VINH5 VINL6 VINH6 VINL7 VINH7 VINL8 VINH8 VCM VRLO VRHI AVDD RST CA MXC A0 A1 A2 EOS RSTI/O CS
7-1851
HI7188
Absolute Maximum Ratings
Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVSS to AVDD Digital Input, Output and I/O Pins . . . . . . . . . . . . . . . DGND to DVDD ESD Tolerance (No Damage) Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only)
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD = +5V, AVSS = -5V, DVDD = +5V, VRHI = +2.5V, VRLO = AGND, VCM = AGND, PGIA Gain = 1, OSCIN = 3.6864MHz, Bipolar Input Range Selected -40oC TO 85oC
PARAMETER SYSTEM PERFORMANCE Resolution Integral Non-Linearity, INL Differential Non-Linearity Offset Error, VOS (Calibrated) Full Scale Error, FSE (Calibrated) Gain Error (Calibrated) Noise, VN(P-P) Common Mode Rejection Ratio, CMRR Off Channel Isolation ANALOG INPUT Common Mode Input Range, VCM Input Leakage Current, IIN Input Capacitance, CIN DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic Current, II Input Capacitance, CIN DIGITAL CMOS OUTPUTS Output Logic High Voltage, VOH Output Logic Low Voltage, VOL (Note 2)
TEST CONDITION
MIN
TYP
MAX
UNITS
Dependent on Gain (Note 2) FS = 25Hz, +FS, +MS, 0, -MS, -FS End Point Line Method (Notes 3, 5, 6) (Note 2) VINHI = VINLO (Notes 3, 4) VINHI - VINLO = +2.5V (Notes 3, 4) Slope = +Full Scale - (-Full Scale) (Notes 3, 4)
-
0.0015
16 0.0045
Bits %FS %FS %FS %FS LSB dB dB
No Missing Codes to 16-Bits 0.0015 0.0015 0.0015 1/4 -75 -
VCM = 0V (Note 5) Delta VCM = 3V (Note 2)
-120
AVSS -
4.0
AVDD 1.0
nA pF
VIN = AVDD (Note 3) (Note 2) See Table 2
2.0 VIN = 0V, +5V VIN = 0V (Note 2) -
1.0 5.0
0.8 10 -
V V A pF
IOUT = -100A (Note 7) IOUT = 3.2mA (Note 7)
2.4 -
-
0.4
V V
7-1852
HI7188
Electrical Specifications
AVDD = +5V, AVSS = -5V, DVDD = +5V, VRHI = +2.5V, VRLO = AGND, VCM = AGND, PGIA Gain = 1, OSCIN = 3.6864MHz, Bipolar Input Range Selected (Continued) -40oC TO 85oC PARAMETER Output Three-State Leakage Current, IOZ Digital Output Capacitance, COUT TIMING CHARACTERISTICS SCLK Minimum Cycle Time, tSCLK (Notes 2, 7) 200 60 50 50 0 100 100 14 75 3.6864 30 1 50 40 40 ns ns ns ns ns ns ns ns ns ns s ns MHz ns s TEST CONDITION VOUT = 0V, +5V (Note 7) (Note 2) MIN TYP 1 10 MAX 10 UNITS A pF
SCLK Minimum Pulse Width, tSCLKPW (Notes 2, 7) CS to SCLK Precharge Time, tPRE Data Setup to SCLK Rising Edge (Write), tDSU Data Hold from SCLK Rising Edge (Write), tDHLD Data Read Access from Instruction Byte Write, tACC Read Bit Valid from SCLK Falling Edge, tDV Last Data Transfer to Data Ready Inactive, t DRDY RESET Low Pulse Width tRESET RSTI/O Low Pulse Width t RSTI/O MUX High Pulse Width tMUX CADDR Valid to MUX High Oscillator Clock Frequency Output Rise/Fall Time Input Rise/Fall Time POWER SUPPLY CHARACTERISTICS IAVDD IAVSS IDVDD Power Dissipation, Active PDA Power Dissipation, Sleep PDS PSRR ( Vsupply = 0.25V) NOTES: 2. Parameter guaranteed by design or characterization, not production tested. AVDD = +5V, OSC1 = 3.6864MHz (Note 3) AVSS = -5V, OSC1 = 3.6864MHz (Note 3) DVDD = +5V, SCLK = 4MHz AVDD = +5V, AVSS = -5V, SLP = `0' (Notes 3, 9) AVDD = +5V, AVSS = -5V, SLP = `1' (Notes 3, 9) PSRR = 20log (Vsupply / VOS ) (Note 3) (Notes 2, 7) (Notes 2, 7) (Notes 2, 7) (Notes 2, 7) (Notes 2, 7) (Notes 2, 7) (Notes 2, 7) (Notes 2, 7) (Notes 2, 7) (Notes 2, 7) (Notes 2, 7) (Notes 2, 7) (Notes 2, 7)
-
1.8 1.8 2.0 28 5 75
3.0 3.0 4.0 50 -
mA mA mA mW mW dB
3. DC PSRR is measured on all supplies individually and applies to both Bipolar and Unipolar Input Ranges. 4. These errors can be removed by re-calibrating at the desired operating temperature. 5. Applies after system calibration. 6. Fully differential input signal source is used. 7. See Load Test Circuit, Figure 1, R1 = 10k, CL = 50pF (Includes Stray and Jig Capacitance). 8. For Line Noise Rejection, 3.6864MHz is required to develop internal clocks to reject 50/60Hz. 9. SLP is the sleep mode enable bit defined in bit 3 of the Control Register (CR <3>).
7-1853
HI7188 Test Circuits
V1
R1 DUT CL (INCLUDES STRAY CAPACITANCE)
FIGURE 1. LOAD TEST CIRCUIT
R1
R2 R1
V
DUT CESD DUT V
R2
DIELECTRIC
HUMAN BODY CESD = 100pF R1 = 10M R2 = 1.5k
MACHINE MODEL CESD = 200pF R1 = 10M R2 = 0 CHARGED DEVICE MODEL R1 = 1G R2 = 1
FIGURE 2. HUMAN BODY AND MACHINE MODEL ESD TEST CIRCUIT
FIGURE 3. CHARGE DEVICE MODEL ESD TEST CIRCUIT
Waveforms
tPRE tSCLK
CS
tDSU SCLK tEN
tSCLKPW
tSCLKPW
tDHLD SDIO 1ST BIT 2ND BIT
FIGURE 4. DATA WRITE TO HI7188
7-1854
HI7188 Waveforms
CS
(Continued)
SCLK
SDIO 1ST BIT SDO tACC tDV 2ND BIT
FIGURE 5. DATA READ FROM HI7188
tEOS EOS
CS
SCLK
SDIO 1 5 6 7 8
FIGURE 6. DATA READ FROM HI7188
Definitions
Integral Non-Linearity (INL) - This is the maximum deviation of any digital code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale (a point 0.5 LSB below the first code transition 000...000 and 000...001) and full scale (a point 0.5 LSB above the last code transition 111...110 to 111...111). Differential Non-Linearity (DNL) - This is the deviation from the actual difference between midpoints and the ideal difference between midpoints (1 LSB) for adjacent codes. If this difference is equal to or more negative than 1 LSB, a code will be missed. Offset Error (VOS) - The offset error is the deviation of the first code transition from the ideal input voltage (VIN - 0.5 LSB). Full Scale Error (FSE) - The full scale error is the deviation of the last code transition from the ideal input full-scale voltage (VIN- + VREF/Gain - 1.5 LSB). Input Span - The input span defines the minimum and maximum input voltages the device can handle while still calibrating properly for gain. End of Scan (EOS) - The end of scan is a signal used to indicate all active logical channels have been converted and data is available to be read. Line Noise Rejection - Line noise rejection is the ability to attenuate (reject) signals at the frequency of power lines typically 50Hz or 60Hz. Physical/Logical Channel - A physical channel pertains to channels which are directly connected to the device package pins identified in the pinout. Logical channels are predefined in the Channel Configuration Registers (CCR) with a physical channels reference (address) being made by the user. Refer to the Channel Configuration Registers section for examples.
7-1855
HI7188 Functional Description
The HI7188 contains a differential 8 channel multiplexer, Programmable Gain Instrumentation Amplifier (PGIA), 4th order sigma-delta ADC, integrating filter, line noise rejection filters, Calibration and data RAMs, bidirectional serial port, clock oscillator, and a microsequencer. The 8 to 1 multiplexer at the input combined with the resetable modulator on the HI7188 allow for conversions of up to 8 differential channels with each channel being updated at a rate of 240 samples per second (with 60Hz line noise rejection enabled). The device can be programmed for conversion of any combination of physical channels. After the signal has passed through the multiplexer, it moves into the PGIA. The PGIA can be configured in gains of 1, 2, 4 and 8 specific for each of the 8 logical channels. The signal then enters the sigma delta modulator. The patented one-shot sigma delta modulator is a fourth order modulator which converts the differential analog signal into a series of one bit outputs. The 1's density of this data stream provides a digital representation of the analog input. The output of the modulator is fed into the integrating low pass digital filter. Data out of the filter is available after 201 bits are received from the modulator. If the device is in line noise rejection mode, the integrating filter data is routed to the Line Noise Rejection filters. This data is then calibrated using the offset and gain calibration coefficients. Data coding is performed and the result is stored in the data RAM. If line noise rejection is disabled, the averaging filter is bypassed, calibration is performed on the data from the integrating filter, the data is coded, and the result is stored in the data RAM. This data flow of modulation, filter and calibrate is repeated for each of the active logical channels (up to 8). After all active logical channels are converted the HI7188 generates an active low interrupt, End Of Scan (EOS), that indicates all logical channels have been updated and valid data is available to be read from the data RAM. Converted data is read via the HI7188 serial I/O port which is compatible with most synchronous transfer formats including both the Motorola SPI and Intel 8051 series SSR protocols. All RAMs, including the Data RAM, are accessed in a "burst" mode. That is, the data for all active logical channels is accessed in a single read communication cycle. When the HI7188 is powered up it needs to be reset by pulling the RST line low. This resets the internal registers as shown in Table 1. This initial configuration defines the part for one active logical channel (physical channel 1, address 000), conversion mode, unipolar operation, gain of one, no line noise rejection, offset binary coding, MSB first I/O bit order, descending I/O byte order, and single line interface. After the RST line returns high, the device immediately begins converting as described above without any further instruction. There is no correction for offset or gain errors on the converted data at this time. To ensure maximum performance, calibration should be done as defined in the operation mode section.
TABLE 1. REGISTER RESET VALUES REGISTER Data Output Registers Channel Configuration Register #2 Channel Configuration Register #1 Control Register Offset Calibration Registers Positive Full Scale Calibration Registers Negative Full Scale Calibration Registers VALUE (HEX) XXXX (undefined) 00XXXXXX XXXXXXXX 0000 000000 800000 800000
The reset configuration should be updated to reflect the users system including chip level and channel level programming. 1. Chip level refers to programming common to all channels such as 50/60 Hertz Line Noise Rejection, number of active channels, etc. and is detailed in the Control Register (CR) section. 2. Channel level programming is custom for each channel such as gain, physical input and mode as detailed in the Channel Configuration Registers (CCR) section. A calibration routine should be performed next to remove system offset and full scale errors (see Calibration section). The CCR is used to place each channel of the device in several operational modes including Conversion, System Offset Calibration, System Positive Full Scale Calibration and System Negative Full Scale Calibration. Each channel inputs should be connected and settled to the correct input condition before the CCR is programmed for each calibration point. After a complete system calibration is performed, the desired analog input is applied and accurate data can be read via the serial interface. The device should be recalibrated when there is a change in the user configuration (i.e. gain, unipolar/bipolar), supply voltage or ambient temperature. The configuration can be saved by writing the contents of the CR, CCR and calibration RAMs to microprocessor system memory (see Serial Interface section). After this has occurred, the configuration can easily be restored back to the HI7188 in the event of power failure or reset.
Using the HI7188
This section describes how to use the device for a typical application. This includes power supply considerations, initial reset, calibration and conversion. Please refer to Figure 7. The analog and digital supplies and grounds are separate on the HI7188 to minimize digital noise coupling into the analog circuitry. Nominal supply voltages are AVDD = +5V, DVDD = +5V, and AVSS = -5V. If the same supply is used for AVDD and DVDD it is imperative that the supply is separately decoupled to the AVDD and DVDD pins on the HI7188. Separate analog and digital ground planes should be maintained on the system board and the grounds should be tied together back at the power supply.
Analog Section Description
The analog portion of the HI7188 consists of a 8 to 1 fully differential Multiplexer, Programmable Gain Instrumentation amplifier (PGIA) and a 4th order Sigma-Delta modulator. Please refer to the simplified analog block diagram in Figure 8.
7-1856
HI7188
(RESET) INITIAL SYSTEM START VIN1H VIN2H VIN3H VIN4H VIN5H VIN6H VIN7H VIN8H PHYSICAL CHANNELS VCM
REFERENCE INPUTS VRHI VRLO
PROGRAM THE SYSTEM LEVEL INFORMATION IN THE CONTROL REGISTER (CR)
APPLY A ZERO SCALE INPUT TO EACH OF THE CHANNELS
PROGRAM THE CHANNEL LEVEL INFORMATION IN THE CHANNEL CONFIGURATION REGISTERS (CCR) AND PLACE EACH CHANNEL IN OFFSET CALIBRATION MODE
PGIA
4TH ORDER
-
DIGITAL SECTION
YES
CA OUTPUT INTERRUPT ACTIVE? NO APPLY A POSITIVE FULL SCALE INPUT TO EACH CHANNEL
VIN1L VIN2L VIN3L VIN4L VIN5L VIN6L VIN7L VIN8L
MODULATOR
CONVERSION CONTROL
FIGURE 8. ANALOG BLOCK DIAGRAM
REPROGRAM THE CCR TO PLACE EACH CHANNEL IN POSITIVE FULL SCALE CALIBRATION MODE
Analog Inputs The analog inputs on the HI7188 are fully differential inputs with programmable gain capabilities. The inputs accept both unipolar and bipolar input signals and gains of 1, 2, 4 or 8. The gain for any given physical channel is independent of the gain of other physical channels. The gain is programmed via the Channel Configuration Register (CCR). The input impedance of the HI7188 is dependent upon the modulator input sampling capacitors which varies with the selected PGIA gain. Table 2 shows the sampling capacitors and input impedances for the different gain settings of the HI7188. Note that this table is valid only for a 3.6864MHz master clock. If the input clock frequency is changed then the input impedance will change accordingly. The equation used to calculate the input impedance is
ZIN = 1/(CS x FS)
YES
CA OUTPUT INTERRUPT ACTIVE? NO APPLY A NEGATIVE FULL SCALE INPUT TO EACH CHANNEL
REPROGRAM THE CCR TO PLACE EACH CHANNEL IN NEGATIVE FULL SCALE CALIBRATION MODE
YES
CA OUTPUT INTERRUPT ACTIVE? NO CONNECT DESIRED ANALOG INPUT, READ DATA RAM VIA SERIAL INTERFACE
Where CS is the internal sampling capacitance and FS is the modulator sampling rate set by the master clock divided by six (FS = 3.6864MHz/6 = 614.4kHz).
TABLE 2. EFFECTIVE INPUT IMPEDANCE vs GAIN SAMPLING RATE (kHz) 614.4 614.4 614.4 614.4 SAMPLING CAPACITOR (pF) 4 8 16 32 INPUT IMPEDANCE (k) 407 203 102 51
NO
EOS OUTPUT INTERRUPT ACTIVE? YES
GAIN 1 2 4 8
NO
RECALIBRATION REQUIRED? YES
FIGURE 7. SYSTEM USAGE FLOWCHART
7-1857
HI7188
Bipolar/Unipolar Input Ranges The inputs can accept either unipolar or bipolar input voltages with each physical channel's mode being independent of other physical channels. Bipolar or unipolar options are chosen by programming the bipolar/unipolar (B/U) bits of the Channel Configuration Registers (CCR). Programming the logical channels for either unipolar or bipolar operation does not change any of the input signal conditioning. The inputs are differential, and as a result are referenced to the voltage on the VINL input. For example, if VINHX is +3.75V and logical channel X is configured for unipolar operation with a gain of 1 and a VREF of +2.5V, the input voltage range on the VINLX input is +1.25V to +3.75V. If VINLX is +1.25V and logical channel X is configured for bipolar mode with gain of 1 and a VREF of +2.5V, the analog input range on the VINHX input is -1.25V to +3.75V. Multiplexer The input multiplexer is a fully differential 8 channel device controlled by the internal microsequencer. Any number of inputs, up to 8, can be scanned and both the number of physical channels scanned and the scanning order are controlled by the users programming of the Channel Configuration Register (CCR). The output of the multiplexer feeds the input to the Programmable Gain Instrumentation Amplifier (PGIA). External Multiplexers For interfacing the HI7188 to external multiplexers several output pins are available. These pins include MXC, A2, A1 and A0. Refer to Figure 9. The MXC pulse is active high during the modulator and integrating filter reset pulse. The pulse width is typically 14.6s with LNR disabled and 54.6s with LNR enabled. This signal can be used to "break before make" an external multiplexer. Referring to Figure 9, the data conversion time involves the actual input channel A/D conversion while the calibration time involves data calibration and coding of the conversion results. The address pins A2, A1 and A0 describe the logical address which is currently being converted. The user can utilize these output pins to drive external multiplexer address pins. The main critical issue is the external multiplexer output must switch and settle to 0.00153% (16 bits) of the final value during the MXC reset pulse and prior to Data Integration or data errors will occur. The input must be stable only during the data integration period but can be changed during the calibration period. Programmable Gain Instrumentation Amplifier The Programmable Gain Instrumentation Amplifier (PGIA) allows the user to interface low level sensors and bridges directly to the HI7188. The PGIA has 4 selectable gain options of 1, 2, 4, and 8. The gain of each physical channel is independent of other physical channels and is programmable by writing the G1 and G0 bits in the Channel Configuration Registers (CCR). Differential Reference Input The reference inputs, VRHI and VRLO , provide a differential reference input capability. VRHI must always be greater than VRLO for proper operation of the device. The common mode range for these differential inputs is from AVSS to AVDD and the nominal differential voltage (VREF = VRHI - VRLO) is +2.5V. Larger values of VREF can be used with minor degradation in performance. Smaller values of VREF can also be used but performance will be degraded since the system noise is larger relative to the LSB size. The full scale range of the HI7188 is defined as: FSRBIPOLAR = 2 x VREF /GAIN FSRUNIPOLAR = VREF/GAIN The reference inputs provide a high impedance dynamic load similar to the analog inputs. For proper circuit operation these pins must be driven by low impedance circuitry. Reference noise outside of the band of interest will be removed by the digital filter but excessive reference noise inside the band of interest will degrade performance. VCM Input The VCM input is the internal reference voltage for the HI7188 analog circuitry and should always be tied to the midpoint of the AVDD and AVSS supplies. This point provides a common mode input voltage for the internal operational amplifiers and must be driven from a low noise, low impedance source if it is not tied to analog ground. Failure to do so will result in degraded HI7188 performance. It is recommended that VCM be tied to analog ground when operating off of AVDD = +5V and AVSS = -5V supplies. VCM also determines the headroom at the upper and lower ends of the power supplies which is limited by the common mode input range where the internal operational amplifiers remain in the linear, high gain region of operation. Sigma Delta Modulator The sigma delta modulator is a fourth order modulator which converts the differential analog signal into a series of one bit outputs. The 1's density of this data stream provides a digital representation of the analog input. Figure 10 shows a simplified block diagram of the analog modulator front end of a Sigma-Delta A/D Converter. The input signal VIN comes into a summing junction (the PGIA in this case) where the previous modulator output is subtracted from it. The resulting signal is then integrated and the output of the integrator goes into the comparator. The output of the comparator is then fed back via a one bit DAC to the summing junction. The feedback loop forces the average of the fed back signal to be equal to the input signal VIN.
DATA CHAN DATA CONVERSION CALIBRATION SWITCH CONVERSION tMXC MXC
CADDR VALID LOGICAL ADDRESS A2, 1, 0
VALID LOGICAL ADDRESS
FIGURE 9. CHANNEL SWITCHING TIMING
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HI7188
PGIA VIN + INTEGRATOR COMPARATOR + -
DAC VRHI VRLO
time the data is transferred to the Line Noise Rejection (LNR) Filters or straight to calibration if LNR is not selected. Line Noise Rejection The line noise rejection section is used to eliminate a periodic sine wave signal of either 50Hz or 60Hz line frequencies. To understand the functionality of the HI7188 line noise rejection (LNR), it is useful to discuss the method utilized by a generic integrating analog to digital converter (ADC). This ADC uses an external summing/integrating capacitor to sum the line noise on a capacitor over one line noise cycle. The cycle period is 16.67ms and 20ms for 60Hz and 50Hz respectively. The ADC output is then the desired input with the line noise summed to zero with a conversion rate equal to the line noise frequency. The HI7188 has the ability to do the same function as the Integrating ADC but samples the input four times during the line cycle (see Figure 12). For this discussion, the desired analog input signal will be zero. The HI7188 accomplishes this by instituting a four quadrant, four point running average system. The microsequencer samples all eight inputs at exactly the same point in time and for the exact amount of time for each of the four quadrants of a single line cycle and stores them separately. These four samples are then summed, on a per channels basis, which results in the same answer of the line synchronous noise as with the Integrating ADC.
16 RAM0 RAM1
FIGURE 10. SIMPLE MODULATOR BLOCK DIAGRAM
Digital Section Description
A block diagram of the digital section of the HI7188 is shown in Figure 11. This section includes an integrating filter, averaging filters, calibration logic registers, output data RAM, digital serial interface and a clock generator. Integrating Filters The integrating filter receives a stream of 1s and 0s from the modulator at a rate of 614kHz. The 1's density of this data stream provides a digital representation of the analog input signal. The integrating filter provides the low pass function with a cutoff of 2kHz. The Integrating Filter works in concert with the modulator and is controlled by the same clock and reset signals. The filter integrates 201 1-bit samples from the modulator for a valid "conversion" to be completed. At that
LOGICAL CHANNELS
LINE NOISE FILTER
BYPASS LNR
CH1 FROM ANALOG SECTION CH2 CH3 CH4 1 CH5 INTEGRATING FILTER 23 CH6 CH7 CH8
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 24
CALIBRATION REGISTERS AND CONTROL
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8
24 CONVERSION CONTROL
16
LOGICAL SEQUENCER
SERIAL INTERFACE CONTROL REGISTER CLOCK GENERATOR
LOGICAL CHANNEL ADDRESS
CCR REGISTERS
EOS CA
RST MODE
CS
SCLK SDO SDIO RSTIO
OSC1 OSC2
FIGURE 11. DIGITAL BLOCK DIAGRAM
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A one channel example: 1. Channel 1 is sampled four times as labeled S1, S2, S3, and S4 in Figure 12. One sample for each 90 degrees quadrant of line cycle (quarter main cycle). 2. Each sample is equally spaced (From zero, S1 = 5 degrees, S2 = 95 degrees, S3 = 185 degrees and S4 = 275 degrees). 3. Each sample is of the same duration of time. 4. Samples S1 and S3 (180 degrees later) will have the equal magnitudes of line noise but have opposite signs. 5. Samples S2 and S4 (180 degrees later) will have the equal magnitudes but opposite signs. 6. The HI7188 sums the samples S1, S3, S2 and S4 which results in averaging the line noise signal to zero. 7. These four samples are placed, real time, in the 4x8 array of registers used for LNR. The next quadrant sampled (S5) replaces S1 in the running average. The new sample replaced S1 at the same point on the line cycle, 5 degrees but 360 degrees later. The line noise summation is still zero. Now for every quarter main cycle thereafter, the LNR will be updated and line noise free output will be available.
5 67 8 12 34 5 6 7 S1 S2 8 TIME 1/4 LINE NOISE 1 S3 2 3 4 5 67 8 3 12 4 5 6 S4 8 7 S5
voltage. It should also be initiated if there is a change in the gain, bipolar, or unipolar input range. The user may choose to ignore data during calibration or check whether any ACTIVE channel is in calibration. Bit 12, the SE bit, of the Control Register offers capability to suppress the EOS interrupt during calibration. If the SE bit is high the EOS interrupt will be suppressed if any active logical channel is in the calibration mode. If the SE bit is high and no active logical channels are in the calibration mode the EOS interrupt will function normally. If low, the suppress EOS function is disabled. To check whether any logical channel is in calibration the user can monitor the Calibration Active (CA) output pin. The CA output pin is high when at least one of the active logical channels are in calibration. If a non active logical channel is in calibration the CA will not be high. The user can monitor the CA pin to determine when all active logical channels are calibrated.
NOTE: When the user accesses the calibration RAMs, via the Serial Interface, the conversion process stops, resetting the modulator, integrating filter and clearing the EOS interrupt. When the calibration RAM I/O operation is completed the device automatically restarts beginning on logical channel 1. The contents of the CR and CCR are not affected by this I/O.
Calibration Time The calibration time varies depending several factors including LNR (50Hz/60Hz) being enabled or disabled, and 2 point calibration. Table 3 contains a summary of the conversion time depending on these factors. Since line noise rejection is a major factor this discussion is divided accordingly.
TABLE 3. CALIBRATION TIME LNR FREQ (Hz) 50 50 60 60 n/a n/a EACH CAL POINT (ms) 20 20 16.7 16.7 N (0.4803) N (0.4803) 40 60 33.3 50.0 2N (0.4803) 3N (0.4803) TOTAL CAL (ms)
3 2 INPUT(V) 1
4
LNR On On On On Off Off
ACTIVE CHANS n/a n/a n/a n/a N N
CAL PNTS 2 3 2 3 2 3
FIGURE 12. LINE NOISE CYCLE INCLUDING PATENTED TIME SPACED INPUT SAMPLING
Calibration
Calibration is the process of adjusting the conversion data based on known system offset and gain errors. For a complete system calibration to occur, the on-chip microcontroller must perform a three point calibration which involves recording conversion results for three different input conditions "zero-scale," "positive full-scale," and "negative full-scale". With these readings, the HI7188 can null any system offset errors and calculate the positive and negative gain slope factors for the transfer function of the system. It is imperative that the zero-scale calibration be performed before either of the gain calibrations. The order of the gain calibrations is not important. Non-calibrated data can be obtained from the device by writing 000000 (h) to the Offset Calibration Register, 800000 (h) to the Positive Full Scale Calibration Register, and 800000 (h) to the Negative Full Scale Calibration Register. This sets the offset of the part to 0 and both the positive and negative gain slope factors to 1. A calibration routine should be initiated whenever there is a change in the ambient operating temperature or supply
NOTE: N is the number of active channels. Total Cal column assumes zero switching time between calibration points.
Line Noise Rejection On When line noise rejection is enabled, it takes 4 conversion scan periods to fill the averaging filters used for attenuating the periodic line noise. A conversion scan involves converting all 8 logical channels at a rate dependent on whether LNR is set to 50Hz or 60Hz. The scan period is 5ms (1/200Hz) and 4.167ms (1/240Hz) respectively. The number of active channels is not applicable in this calculation since the microsequencer converts on ALL logical channels to maintain LNR timing regardless of the number of user defined active channels.
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HI7188
Line Noise Rejection Off Operation of the device is altered slightly when LNR is disabled. Since the microsequencer is not synchronizing for any line noise, the conversion rate increases to 260.3 conversions second/channel (10% increase). With LNR disabled, a conversion scan involves converting only the ACTIVE logical channels. When ACTIVELY converting on less than 8 channels, this is the major speed advantage over LNR enabled which sets conversion scan period based on ALL eight logical channels. Refer to Table 3. System Offset Calibration The system offset calibration mode is a process that allows the user to lump offset errors of external circuitry and the internal errors of the HI7188 together and null them out. This mode will convert the external differential signal applied to the VIN inputs and then store that value in the offset calibration RAM for that physical channel. To invoke the system offset calibration the user applies the "zero scale" voltage to the physical channel requiring calibration, then writes the related CCR byte indicating offset calibration is required. The next time this logical channel is converted, the microsequencer performs calibration and updates the related offset RAM. Next the internal microsequencer places that logical channel back into the conversion mode and updates the CCR byte. System Positive Full Scale Calibration The system positive full scale calibration mode is a process that allows the user to lump positive gain errors of external circuitry and the internal gain errors of the HI7188 together to calculate the positive transfer function of the system. This mode will convert the external differential signal applied to the VIN inputs and then store that value in the system positive full Scale calibration RAM for that physical channel. To invoke the system positive full scale calibration the user applies the "positive full scale" voltage to the physical channel requiring calibration, then writes the related CCR byte indicating positive full scale calibration is required. The next time this logical channel is converted, the microsequencer performs calibration and updates the related system positive full scale calibration RAM. Next the internal microsequencer places that logical channel back into the conversion mode and updates the CCR byte. System Negative Full Scale Calibration The system negative full scale calibration mode is a process that allows the user to lump negative gain errors of external circuitry and the internal gain errors of the HI7188 together to calculate the negative transfer function of the system. This mode will convert the external differential signal applied to the VIN inputs and then store that value in the system negative full scale calibration RAM for that physical channel. To invoke the system negative full scale calibration the user applies the "negative full scale voltage", which must be equal to Vref, to the physical channel requiring calibration, then writes the related CCR byte indicating negative full scale calibration is required(see note below). The next time this logical channel is converted, the microsequencer performs calibration and updates the related system negative full scale calibration RAM. Next the internal microsequencer places that logical channel back into the conversion mode and updates the CCR byte. TEMPORARY NOTE: In bipolar mode, the user MUST perform negative full scale calibration with the exact differential voltage applied to the Vref pins, otherwise large errors will occur at the zero crossing point. During normal conversions, the error occurs when the input is at the offset calibration point. At this point, plus or minus 1/2 LSB, the output code will be either the true half scale reading of 7FFF/8000 (offset binary coding) or negative full scale 0000. This problem has been corrected with the HI7188A. Offset and Gain Adjust Limits Whenever a calibration mode is used, there are limits to the amount of offset and gain which can be adjusted. For both bipolar and unipolar modes the minimum and maximum input spans are 0.2 x VREF/GAIN and 1.2 x VREF/GAIN respectively. In the unipolar mode the offset plus the span cannot exceed the 1.2 x VREF/GAIN limit. So, if the span is at its minimum value of 0.2 x VREF/GAIN, the offset must be less than 1 x VREF/GAIN. In bipolar mode the span is equidistant around the voltage used for the zero scale point. For this mode the offset plus half the span cannot exceed 1.2 x VREF/GAIN. If the span is at 0.2 x VREF/GAIN, then the offset can not be greater than 2 x VREF/GAIN.
Range Detection
In addition to the calibration process, the converter detects over range above positive full scale and under range below minus full scale conditions. Over or under range detection affects the output data coding as described in the Data Coding section. Over range detection is identical for both bipolar and unipolar operation. Over range is detected by comparing the offset corrected filter output to the positive gain coefficient. If the current offset corrected filter value is greater than the positive gain coefficient, an over range condition is detected. In unipolar mode, under range is detected by sampling the sign bit of the offset calibrated data. If the sign bit is logic 1, signifying a negative voltage, an under range condition exists. In bipolar mode, under range is detected by comparing the offset corrected filter output to the negative gain coefficient. If the current offset corrected filter value is less than the negative gain coefficient, an under range condition is detected.
Data Coding
The calibrated data can be obtained in one of various numerical codes depending on the bipolar/unipolar mode bit and the two's complement coding bit. In bipolar mode, if the two's complement bit is high, the output is two's complement. In bipolar mode, offset binary coding is used when the two's complement coding bit is low. In unipolar mode, only binary coding is available and the two's complement coding bit is a don't care. The output coding for the HI7188 is shown in Tables 4 and 5. VZS represents the applied zero scale input during system offset calibration. VPFS represents the applied positive full scale input during system positive full scale calibration. VNFS represents the applied negative full scale input during system negative full scale calibration.
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HI7188
TABLE 4. BIPOLAR MODE OUTPUT CODES (HEX) TWO'S COMPLEMENT CODE 7FFF 7FFF/7FFE 0000/FFFF 8001/8000 8000 OFFSET BINARY CODE FFFF FFFF/FFFE 8000/7FFF 0001/0000 0000
INPUT VOLTAGE >(VPFS - 1.5 LSB) VPFS - 1.5 LSB VZS - 0.5 LSB VNFS + 0.5 LSB <(VNFS + 0.5 LSB)
2. The data RAM (RAM0 containing N data) read has been started but is not complete, the read pointer remains with RAM0 and the write pointer remains with RAM1. This has the effect of overwriting conversion N+1 with N+2 before N+1 can be read, therefore conversion N+1 is lost.
Clocking/Oscillators
The master clock of the HI7188 can be supplied by either a crystal connected between the OSC1 and OSC2 pins as shown in Figure 13A or a CMOS compatible clock signal connected to the OSC1 pin as shown in Figure 13B and floating the OSC2 pin. The master clock is used by the internal clock generator to derive the clock edges required for both analog and digital sections. The HI7188 is designed or a 3.6864MHz clock to maintain Line Noise Rejection.
TABLE 5. UNIPOLAR MODE DATA OUTPUT CODES (HEX) INPUT VOLTAGE >(VPFS - 1.5 LSB) VPFS - 1.5 LSB VPFS/2 - 0.5 LSB VZS + .5 LSB <(VZS + 0.5 LSB) BINARY CODE FFFF FFFF/FFFE 8000/7FFF 0001/0000 0000
Crystal Operation
Using a crystal to generate the clock, care must be taken to minimize any external stray capacitance/inductance seen by the OSC1 and OSC2 pins. If care is not taken, the feedback (crystal) loop noise will result in a non reliable master clock, which in turn, will produce erroneous conversion results. The crystal should be connected as close to the HI7188 device as physically possible. If you cannot meet these requirements, we would recommend you use an External CMOS Clock instead of the crystal. External CMOS Clock Operation When driving the HI7188 with an external CMOS clock, the clock should never be turned off. If the clock is turned off, the device should be re-synchronized by resetting either manually via the RESET pin or by the following special software instructions. If the device is not re-synchronized erroneous conversion results may be observed. The hardware reset will clear all registers and RAMs as defined in the data sheet. The software reset is achieved by either performing an I/O access of any calibration RAM or cycling the device through a sleep cycle. Calibration RAM Access To re-synchronize the conversion process the user may perform an I/O access of any calibration RAM (read or write). When the user performs this I/O access the microsequencer stops the conversion process, resets the modulator, digital filter and waits until the I/O is complete. After the I/O is completed the microsequencer automatically restarts the conversion process. Sleep Cycle Another method to re-synchronize the conversion process is to cycle the device through a sleep cycle. The user places the device in SLEEP mode by writing the SLP bit (CR<3>) of the Control Register to logic one. The microsequencer will stop the conversion process, reset the conversion pointer to logical channel one, clear the four line noise rejection filters and deactivate EOS. The serial interface, calibration/data RAMs, CR and CCR are not affected. To return from sleep mode the user changes the SLP bit from high to low. This restarts the conversion process beginning with logical channel 1. If line noise rejection (LNR) is enabled, it takes four complete scans (all eight channels) to
When the range detection logic determines an over range, the converter output will clamp at the >(VPFS - 1.5 LSB) output as described in Tables 4 and 5. When the range detection logic determines an under range, the converter output will clamp at the <(VNFS + 0.5 LSB) output described in Table 4 or the <(VZS + 0.5 LSB) output described in Table 5.
Data RAM
The Data RAM block is comprised of two 8 x 16 memory elements which store conversion results after calibration and data coding. Two RAMs are required to allow a one channel scan buffer per logical channel. The user can only READ from the data RAM. For illustration, these elements are labeled RAM0 and RAM1. The RAMs are configured such that when one is internally writable the other is readable via serial I/O. The following paragraphs describe the data RAM operation. Please refer to the Functional Block Diagram. For example, from initialization, RAM0 is writable, RAM1 is readable, EOS is inactive. Conversion completes on all active logical channels (RAM0 stores conversion N data) and the EOS interrupt is generated. Internally, the microsequencer switches RAM0 to readable, RAM1 to writable. The user can read the data RAM to obtain N conversion results, clearing the EOS interrupt. The next conversion N+1 completes on all active logical channels (RAM1 stores N+1 data). If a data RAM (RAM0 containing N data) read has been completed before the N+1 conversion scan has completed, RAM1 will switch to being readable and RAM0 is writable. This is normal operation and no conversion results are lost. If the data RAM (RAM0 containing N data) is not completely read before the N+1 conversion is completed, there are two possible results. 1. The data RAM read has not been started (RAM0 containing N data), EOS remains active low and the microsequencer will switch RAM1 to be readable and RAM0 to be writable. This has the effect of overwriting conversion N with N+2.
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HI7188
refill the four line noise rejection filters before an EOS interrupt. If LNR is not enabled, it takes one conversion scan of only the active channels before an EOS interrupt. Recalibration is not required since the calibration RAMs are not effected by the sleep operation.
X-3.6864MHz 5 OSC1 HI7188 6 OSC2
processors which allow an external device to clock their serial port. The frequency of SCLK is one eighth of the external crystal connected between the OSC1 and OSC2 pins. The HI7188 is designed for a 3.6864MHz crystal which sets SCLK to 460.8kHz. Synchronous External Clocking The HI7188 is in a external clocking scheme if the MODE pin is low. This defines the SCLK pin as an input and an external clock must be provided to the SCLK pin. This external clocking mode is designed for direct interface to systems which provide a serial clock output which is synchronized to the serial data output. The maximum frequency of the external SCLK is 5MHz. Burst RAM Access The Data RAM, System Offset calibration RAM, System Positive Full Scale Calibration RAM and System Negative Full Scale Calibration RAM can only be accessed in a continuous RAM "Burst". RAM burst transfers are special instructions that perform a continuous data transfer for all bits of that RAM. That is, individual bytes of any RAM cannot be accessed without reading all of the bytes. See Table 7. Each transfer occurs such that the first word transferred corresponds to the first logical channel converted as specified in the Channel Configuration Register (CCR). The first byte transferred for each word is controlled by the RB bit of the instruction byte and the bit position is determined by the Control Register (CR) MSB/LSB bit. The number of words transferred is specified by the CR bits that describe the number of logical channels being converted as well as the size of the destination RAM. This transfer mode reduces the overhead of multiple IR writes as compared to individual byte access. The following two examples are useful in understanding the RAM burst transfer instructions. Example 1. The physical channel conversion order as specified by the CCRs is 8, 2, 3, 4, 5, 6, 1, 7. The HI7188 is setup via the Control Register to convert 8 logical channels. The IR byte written is 0xx11100 (read the data RAM). The following occurs: After completing the IR write, 16 bytes of data will be transferred from the HI7188. The first byte transferred will be the most significant byte of the physical channel 8 conversion results. The second byte will be the least significant byte of the physical channel 8 conversion results. This pattern of most significant byte followed by least significant byte will repeat, in order for physical channels 2, 3, 4, 5, 6, 1, 7. Example 2. The physical channel conversion order as specified by the CCRs is 8, 2, 3, 4, 5, 6, 1, 7. The HI7188 is setup via the Control Register to convert only 3 logical channels. The IR byte written is 1xx01101 (write the offset RAM). The following occurs: After completing the IR write, 9 bytes of data will be written to the offset RAM (recall that the Offset Calibration register is 3 bytes wide). The first byte is the least significant byte used for offset calibration of physical channel 8. The second byte will be the middle byte used for offset calibration of physical channel 8. The third byte will be the most significant byte used for offset calibration of physical channel 8. This pattern of least significant byte to most significant byte will repeat for all logical channels converted in the logical channel order as described above. For example, the last byte transferred will be the most significant byte of physical channel 3 used for offset calibration.
FIGURE 13A. Crystal Operation
NOT CONNECTED 5 OSC1 HI7188 6 OSC2
X-3.6864MHz
FIGURE 13B. External CMOS clock operation
Serial Interface
The HI7188 has a flexible, synchronous serial communication port to allow easy interfacing to most industry standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola 6805/11, SPI and Intel 8051 SSR protocols. The interface supports 2-wire transfers of reading and writing on a single bidirectional line (SDIO) or 3-wire transfers of writing on SDIO and reading on the SDO line. The Interface allows read/write access to the Control Register, Channel Configuration Registers, and Calibration RAMs. The interface allows read only access to the data RAM (refer to Table 7). The interface is byte organized with each register byte having a specific address. Single or multiple byte transfers are supported. In addition, the interface allows flexibility as to the byte and bit access order. That is, the user can specify MSB/LSB first bit positioning and can access bytes in ascending/descending order from any byte position. Serial Interface Clock The HI7188 supports two serial interface clock(SCLK) modes for all interface timing. This allows the greatest flexibility for different types of systems where the HI7188 can act either as master in the system (it provides the serial interface clock) or as slave (an external clock is provided to the HI7188). These two modes are defined as self clocking and external clocking respectively. Regardless of the clocking mode selected, all data is registered into the HI7188 on the rising edge of the SCLK while all data is driven out on the falling edge of SCLK. The HI7188 interface is designed to work with clock stalling in either high or low state. The clock mode is determined by the logic level applied to the MODE pin. Synchronous Self Clocking The device in a self-clocking scheme if the MODE pin is high. This defines the SCLK pin as an output which provides the serial clock signal used for the transfer of all data to and from the HI7188. This self-clocking mode can be used with
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NOTE: When the user accesses the calibration RAMs, via the Serial Interface, the conversion process stops, resetting the modulator, integrating filter and clearing the EOS interrupt. When the calibration RAM I/O operation is completed the device automatically restarts beginning on logical channel 1. The contents of the CR and CCR are not affected by this I/O. TABLE 7. INTERNAL REGISTER ADDRESS (Continued) NB1, R/W NB0 IR [7] IR [6:5] 0/1 0/1 0/1 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 xx xx xx xx xx xx xx xx A3, A2, A1, A0 IR [3:0] 0101 0110 0111 0100 0101 0110 0111 0100 0101 0110 0111 0100 0101 0110 0111 1000 1001 1010 1011 1000 1001 1010 1011 1000 1001 1010 1011 1000 1001 1010 1011 1100 1100 1101 1101 1110 1110 1111 1111
DESCRIPTION CCR #1, start byte 1, 1 byte transfer CCR #1, start byte 2, 1 byte transfer CCR #1, start byte 3, 1 byte transfer CCR #1, start byte 0, 2 byte transfer CCR #1, start byte 1, 2 byte transfer CCR #1, start byte 2, 2 byte transfer CCR #1, start byte 3, 2 byte transfer CCR #1, start byte 0, 3 byte transfer CCR #1, start byte 1, 3 byte transfer CCR #1, start byte 2, 3 byte transfer CCR #1, start byte 3, 3 byte transfer CCR #1, start byte 0, 4 byte transfer CCR #1, start byte 1, 4 byte transfer CCR #1, start byte 2, 4 byte transfer CCR #1, start byte 3, 4 byte transfer CCR #2, start byte 0, 1 byte transfer CCR #2, start byte 1, 1 byte transfer CCR #2, start byte 2, 1 byte transfer CCR #2, start byte 3, 1 byte transfer CCR #2, start byte 0, 2 byte transfer CCR #2, start byte 1, 2 byte transfer CCR #2, start byte 2, 2 byte transfer CCR #2, start byte 3, 2 byte transfer CCR #2, start byte 0, 3 byte transfer CCR #2, start byte 1, 3 byte transfer CCR #2, start byte 2, 3 byte transfer CCR #2, start byte 3, 3 byte transfer CCR #2, start byte 0, 4 byte transfer CCR #2, start byte 1, 4 byte transfer CCR #2, start byte 2, 4 byte transfer CCR #2, start byte 3, 4 byte transfer Data RAM burst transfer, least significant byte first, READ ONLY Data RAM burst transfer, most significant byte first, READ ONLY Offset RAM burst transfer, least significant byte first. Offset RAM burst transfer, most significant byte first. Positive full scale RAM burst transfer, least significant byte first. Positive full scale RAM burst transfer, most significant byte first. Negative full scale RAM burst transfer, least significant byte first. Negative full scale RAM burst transfer, most significant byte first.
Detailed Register Descriptions
Instruction Register The instruction register is an 8 bit register which is used during a communications cycle for setting up read/write operations. Below are the bit assignments.
INSTRUCTION REGISTER (BYTE) MSB R/W 6 NB1 5 NB0 4 RB 3 A3 2 A2 1 A1 LSB A0
0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0 0 0/1 0/1 0/1 DESCRIPTION CR, start byte 0, 1 byte transfer CR, start byte 0, 2 byte transfer CR, start byte 1, 1 byte transfer CR, start byte 1, 2 byte transfer CCR #1, start byte 0, 1 byte transfer 0/1 0/1 0/1
R/W - Bit 7 of the Instruction Byte determines whether phase 2 of the communication cycle will be a read or write operation. If R/W is logic 1, a write transfer will occur in phase 2 of the communication cycle. If R/W is logic 0, a read transfer will occur in phase 2 of the communication cycle. NB1, NB0 - Bits 6 and 5 of the Instruction Byte determine the number of bytes that will be transferred during phase 2 of a communication cycle, if a register is selected for I/O access. If a RAM is selected for IO access, these bits are don't care. Any number of bytes from 1 to 4 is allowed. See Tables 6 and 7.
TABLE 6. MULTIPLE BYTE ACCESS BITS NB1, NB0 IR [6:5] 00 01 10 11 DESCRIPTION Transfer 1 Byte Transfer 2 Bytes Transfer 3 Bytes Transfer 4 Bytes
RB - Bit 4 is used to determine the byte order when accessing a RAM address. When accessing a RAM address, if RB = 1, the data format is most significant byte first to least significant byte. When accessing a RAM address, if RB = 0, the data format is least significant byte first to most significant byte. When accessing a register address, this bit is a don't care. A3, A2, A1, A0 - Bits 3 and 2 (A3 and A2) of the Instruction Byte determine which of the three internal registers will be accessed or if both bits are set (11b), that a RAM access is active. For register addresses, bits 1 and 0 (A1 and A0) determine which byte of that register will be accessed first. For RAM access (A3 = 1, A2 = 1), bits 1 and 0 (A1 and A0) determine which RAM is the source or destination.
TABLE 7. INTERNAL REGISTER ADDRESS NB1, R/W NB0 IR [7] IR [6:5] 0/1 0/1 0/1 0/1 0/1 00 01 00 01 00 A3, A2, A1, A0 IR [3:0] 0000 0000 0001 0001 0100
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HI7188
Control Register The Control Register (CR) is 16 bits wide and contains information that determines operating mode and the system/chip level configuration. This configuration applies to all logical channels and cannot be modified at the channel level. Following are the bit assignments:
CONTROL REGISTER BYTE 1 MSB T3 14 T2 13 T1 12 CHOP 11 SE 10 LNR 9 FS LSB TC TABLE 8. NUMBER OF CONVERSION CHANNELS N2, N1, N0 CR [7:5] 000 001 010 011 100 101 110 111 MSB N2 6 N1 5 N0 4 TP 3 SLP 2 BD 1 MSB LSB SDL NUMBER OF CHANNELS TO CONVERT 1 2 3 4 5 6 7 8
CONTROL REGISTER BYTE 0
T3, T2, T1 - Bits 15, 14 and 13 are reserved and MUST always be logic zero for normal operation. These bits are low after RESET is applied. CHOP. Bit 12 is the active low chop bit used to determine whether the chopper stabilized amplifier is used or bypassed. This bit is low (chop on) after RESET is applied. SE. Bit 11 is the active high suppress EOS bit. If high, the EOS interrupt will not go active when any logical channel is in calibration mode. If this bit is high and no logical channels are in the calibration mode, or this bit is low, EOS functionality is as previously described. This bit allows the user to suppress false EOS interrupts during calibration. Only logical channels that are actively being converted are considered. That is, if only two logical channels are being converted but the CCR byte for a non active logical channel is in a calibration mode, the EOS functionality is active. This bit is low (suppress EOS off) after RESET is applied. LNR. Bit 10 is the active high line noise rejection(LNR) bit. If high LNR is selected. This bit is low (LNR off) after RESET is applied. FS. Bit 9 is the 50Hz/60Hz frequency select bit. If bit 9 is high, the clock generation logic synchronizes conversions for proper rejection of 50Hz line noise. If bit 9 is low, the clock generation logic synchronizes conversions for proper rejection of 60Hz line noise. This bit is low (60Hz LNR) after RESET is applied. TC. Bit 8 is the active high two's complement bit used to select between 2's complementary and offset binary data coding for bipolar mode. In bipolar mode, a high selects two's complement; when low data is offset binary. Note that in unipolar mode the binary data coding is not affected by the TC bit. This bit is low (offset binary data) after RESET is applied. N2, N1, N0. Bits 7, 6 and 5 are the bits that specify the number of active logical channels to be converted. See Table 8. These bits are low (one active channel) after RESET is applied.
TP - Bit 4 is the active high two point calibration bit. When high, the positive gain slope factor is used for both positive and negative voltages. This bit is low (normal three point cal) after RESET is applied. SLP - Bit 3 is the active high sleep mode bit used to put the device in a low power/standby mode. When high, conversion stops and the conversion pointer is reset to logical channel 1. The four line noise rejection filters are cleared and EOS is deactivated. The serial interface, calibration/data RAMs, CR and CCR are not affected. To return from sleep mode the user changes this bit from high to low. This restarts the conversion process beginning with logical channel 1. If line noise rejection is enabled, it takes four complete scans (all active channels) to refill the four line noise rejection filters before an EOS interrupt. If line noise rejection not enabled, it takes 1 complete scan before an EOS interrupt. This bit is low (sleep mode off) after RESET is applied. BD. Bit 2 is the byte direction bit used to determine either ascending or descending order access for multi-byte transfers. When high, ascending order is enabled. When low, descending order is enabled. This bit is low (descending order) after RESET is applied. MSB. Bit 1 bit direction bit used to select whether a serial data transfer is MSB or LSB first. When low, MSB first mode is enabled while high selects LSB first. This bit is low (MSB first) after RESET is applied. SDL. Bit 0 selects a two-wire or three-wire transfer protocol of the serial interface. When low, two-wire data transfers are done using the SDIO pin. Both data in and out of the part is uses the by-directional SDIO pin. When high, three-wire data transfers are done using the SDIO and SDO pins. Data into the part uses the SDIO pin while data out uses the SDO pin. This bit is low (two-wire, SDIO exclusively) after RESET is applied. Channel Configuration Registers The HI7188 Channel Configuration Registers (CCR) comprise a 64-bit memory element that defines the logical channel conversion order as well as each logical channel specific data such as physical channel address, mode, gain, and bipolar/unipolar operation. The 64 bits are divided into two 32 bit register blocks referred to as CCR#2 and CCR#1. Each register contains four
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HI7188
bytes pertaining to four logical channels. The register may be accessed 1, 2, 3 or 4 bytes at a time. Please refer to Table 10 to determine physical address assignments within the CCR and Table 9 for logical channel assignment. The physical channel conversion order is defined based on it's location in the CCR blocks. For example, if the CCR #2 <31:24> is set with the CCR <2:0> = 100, then physical channel 5 will be converted first. The CCR is byte wide accessible via the Serial Interface allowing the user to change the individual logical channel configuration on the fly. Following are the bit assignments.
TABLE 9. CHANNEL CONFIGURATION REGISTER BLOCK CCR #2 CCR #2 CCR #2 CCR #2 CCR #1 CCR #1 CCR #1 CCR #1 BIT LOCATION <31:24> <23:16> <15:8> <7:0> <31:24> <23:16> <15:8> <7:0> DESCRIPTION 1st Logical Channel 2nd Logical Channel 3rd Logical Channel 4th Logical Channel 5th Logical Channel 6th Logical Channel 7th Logical Channel 8th Logical Channel TABLE 11. HI7188 OPERATIONAL MODES MD1 0 0 1 1 MD0 0 1 0 1 OPERATIONAL MODE Conversion System Offset Calibration System Positive Full Scale Calibration System Negative Full Scale Calibration
G1, G0 - Bit 1 and 0 defines the PGIA gain of 1, 2, 4 or 8. Please refer to Table 12.
TABLE 12. CHANNEL GAIN G1, G0 CCR [1:0] 00 01 10 11 PGIA CHANNEL GAIN 1 2 4 8
Serial Interface Pin Description The serial I/O port is a bidirectional port which is used to read and write the internal registers. The port contains two data lines, a synchronous clock, and two status flags. Figure 14 shows a diagram of the serial interface lines.
DATA OUT BIDIRECTIONAL DATA SDO SDIO SCLK CS EOS CA MODE RSTI/O HI7188
CHANNEL CONFIGURATION REGISTER (BYTE) MSB CH2 6 CH1 5 CH0 4 B/U 3 MD1 2 MD0 1 G1 LSB G0
PORT CLOCK CHIP SELECT END OF SCAN
CH2, CH1, CH0 - Bits 7, 6, 5 of the channel configuration byte determine which physical inputs are used as shown in Table 10.
TABLE 10. ACTIVE CHANNEL DECODE CH2, CH1, CH0 CCR [2:0] 000 001 010 011 100 101 110 111 PHYSICAL INPUT PINS VINH1, VINL1 VINH2, VINL2 VINH3, VINL3 VINH4, VINL4 VINH5, VINL5 VINH6, VINL6 VINH7, VINL7 VINH8, VINL8
CALIBRATION ACTIVE CLOCK MODE RESET I/O
FIGURE 14. HI7188 SERIAL INTERFACE
SDO - Serial Data Out. Data is read from this line using those protocols with separate lines for transmitting and receiving data. An example of such a standard is the Motorola Serial Peripheral Interface (SPI) using the 68HC05 and 68HC11 family of microcontrollers, or other similar processors. In the case of using bidirectional data transfer on SDIO, the SDO does not output data and is set in a high impedance state. SDIO - Serial Data In or Out. Data is always written to the device on this line. However, this line can be used as a bidirectional data line. This is done by properly setting up the Control Register. Bidirectional data transfer on this line can be used with Intel standard serial interfaces (SSR, Mode 0) in MCS51 and MCS96 family of microcontrollers, or other similar processors. SCLK - Serial Clock. The serial clock pin is used to synchronize data to and from the HI7188 and to run the port state machines. In Synchronous External Clock Mode, SCLK is configured as an input, is supplied by the user, and can run up to a 5MHz rate. In Synchronous Self Clocking Mode, SCLK is configured as an output and runs at OSC1/8 = 460.8kHz.
B/U - Bit 4 of the channel configuration byte determine bipolar or unipolar mode. If Logic 1, bipolar mode is selected while logic 0 selects unipolar mode. MD1, MD0 - Bit 3 and 2 of the channel configuration byte are the channel Mode bits. This defines the mode of operation for that logical channel, please see Table 11. All calibration modes automatically return to conversion mode after calibration is complete.
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CS - Chip Select. This signal is an active low input that allows more than one device on the same serial communication lines. The SDO and SDIO will go to a high impedance state when this signal is high. If driven high during any communication cycle, that cycle will be suspended until CS reactivation. Chip select can be tied low in systems that maintain control of SCLK. EOS - End Of Scan. Signals the end of a logical channel scan (all programmed logical channels have been converted) and data is available for reading. EOS is useful as an edge or level sensitive interrupt signal to a microprocessor or microcontroller. EOS low indicates that new data is available and the Data RAM can be read. EOS will return high upon completion of a complete Data RAM read cycle. Please refer to the Data RAM section for details. CA - Calibration Active. This pin is high if any active logical channel is in the calibration mode and stays high for the entire scan period. CA checks only those channels that are actively being converted on. For example, if the HI7188 is programmed to convert only two channels and any of the CCR bytes of the six nonactive channels are in the calibration mode, CA will NOT go active. The user can monitor the CA output to determine when all active channels have completed calibration. MODE - Mode. This input is used to select between Synchronous Self Clocking Mode (high) or the Synchronous External Clocking Mode (low). RSTI/O - Reset I/O. This active low asynchronous input is used to reset the serial interface state machine. This reset only affects the I/O logic and does not affect the Control Register, Channel Configuration Register or Calibration RAMs. This effectively aborts any communication cycle and places the device in a standby mode awaiting the next IR cycle. Serial Interface Communication It is useful to think of the HI7188 interface in terms of communication cycles. Each communication cycle happens in 2 phases. The first phase is the writing of an instruction byte while the second phase is the data transfer as described by the instruction byte. It is important to note that phase 2 of the communication cycle can be a single byte or a multi-byte transfer of data including a Burst RAM read/write. It is up to the user to maintain synchronism with respect to data transfers. If the system processor "gets lost", during an I/O operation, the only way to recover is to reset the Serial Interface via a RSTI/O. Figure 15 shows both a 2-wire and a 3-wire data transfer. Instruction Byte Phase The instruction byte phase initiates a data transfer sequence. The processor writes an eight bit byte to the "Instruction Register", known as the "Instruction Byte". The instruction byte informs the HI7188 about the Data cycle phase activities and includes the following information: * Read or Write Cycle * Number of Bytes to be Transferred * Which Register and Starting Byte to be Accessed
DATA CYCLE CS INSTRUCTION BYTE SDIO INSTRUCTION CYCLE SDO DATA BYTE 1 DATA BYTE 2 DATA BYTE 3
Data Cycle Phase In the data cycle phase, data transfer takes place as defined by the Instruction Register Byte. See Write Operation and Read Operation sections for detailed descriptions. It is important to note that phase 2 of the communication cycle can be a multi-byte transfer of data. For example, the 4 byte Channel Configuration register can be read using one multi-byte communication cycle rather than four single byte communication cycles. After phase 2 is completed the HI7188 I/O logic enters a standby mode while waiting to receive a new instruction byte. It is up to the user to maintain synchronism with respect to data transfers. If the system processor "gets lost" the only way to recover is to reset the HI7188. Serial Interface Format Several formats are available for reading from and writing to the HI7188 registers in both the 2-wire and 3-wire protocols. Please refer to Figure 15. A portion of these formats is controlled by the CR<2:1> (BD and MSB) bits which control the byte direction and bit order of a data transfer respectively. These two bits can be written in any combination but only the two most useful will be discussed here. The first combination is to reset both the BD and MSB bits (BD = 0, MSB = 0). This sets up the interface for descending byte order and MSB first format. When this combination is used the user should always write the instruction register such that the starting byte is the most significant byte address. For example, read three bytes of data starting with the most significant byte. The first byte read will be the most significant in MSB to LSB format. The next byte will be the next least significant (recall descending byte order) again in MSB to LSB order. The last byte will be the next lesser significant byte in MSB to LSB order. THE ENTIRE WORD WAS READ MSB TO LSB format. The second combination is to set both the BD and MSB bits to 1. This sets up the interface for ascending byte order and LSB first format. When this combination is used the user should always write the instruction register such that the starting byte is the least significant byte address. For example, read three bytes of data starting with the least significant byte. The first byte read will be the least significant in LSB to MSB format. The next byte will be the next greater significant (recall ascending byte order) again in LSB to MSB order. The last byte will be the next greater significant byte in LSB to MSB order. THE ENTIRE WORD WAS READ LSB TO MSB format. After completion of each communication cycle, The HI7188 interface enters a standby mode while waiting to receive a new instruction byte.
FIGURE 15. 3-WIRE, 3 BYTE READ TRANSFER
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HI7188 Die Characteristics
DIE DIMENSIONS: 215 mils x 257 mils (5466m x 6536m) METALLIZATION: Type: AlSiCu Thickness: Metal 2 16kA Metal 1 6kA SUBSTRATE POTENTIAL: AVSS WORST CASE CURRENT DENSITY: <2.0 x 105 A/cm2 PROCESS: HBCIO PASSIVATION: Type: Sandwich Nitride Thickness: 8kA USG Thickness: 1kA
Metallization Mask Layout
HI7188
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